[j-nsp] M10i FPC PIC Throughput Questions

[Matt Bentley]

OK - so there has been a lot of discussion around this that I've seen, but
I've searched for hours and still can't find concrete answers.  Can someone
help?

1.  Does the 3.2 Gbps throughput limitation include overhead?  In other
words, Is the "raw" throughput 4 Gbps with effective throughput of 3.2
Gbps?  Or is it 3.2 Gbps of raw throughput with effective throughput of 2.5
Gbps?
2.  Is this throughput per PIC on the FPC?  So let's say I have three 4x
GigE IQ2 PICs and one channelized DS3 IQ PIC.  Does each PIC get bandwidth
allocated equally between them?  So is it 800 Mbps per PIC, and the PICs
can't "steal" bandwidth from another one?
3.  Where, and based on what, is traffic dropped with  Juniper head of line
blocking (ie where multiple high speed input interfaces try to go out the
same lower speed exit interface)?

Thanks very much!