[j-nsp] RIB and FIB - Memory for MX with LR

[Morgan McLean]

On Thursday, June 27, 2013, joel jaeggli wrote:

> On 6/27/13 8:14 PM, Giuliano Medalha wrote:
>
>> People,
>>
>> Thinking about configuring 2 Logical Systems in a MX480 box with RE1800X4,
>> how can we provide control for memory allocation ?
>>
>> The box has the following configuration:
>>
>> 2 x RE1800X4-16GB
>> 1 x MPC-3D-16XGE-SFPP-R-B
>> 2 x SCBE-MX
>>
>> Is it possible to control the RIB and the FIB size using JUNOS for each
>> Logical System ?
>>
> you can control was get's installed in the fib directly using policy...
>
> my lab logical system route reflectors use something like this to limit
> what they install in the fib
>
> routing-options {
> ...
> forwarding-table {
> export [ logical-system-fib-compress reject-all ];
> }
> }
>
> policy-options {
>
> policy-statement logical-system-fib-compress {
> from protocol [ direct static isis ];
> then accept;
> }
> policy-statement reject-all {
> then reject;
> }
>
> }
>
> which means the bgp rib can grow to fairly outlandish size and not crap up
> the fib associated with that logical system.
>
> obviously you can be a little more fine grained.
>
>  Or is it automatic by the system ?
>>
>> How much routes is possible in FIB for MX480 ?  2.5M ?  For this board
>> when
>> create logical system it divide by two ?
>>
>> Thanks a lot,
>>
>> Giuliano
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>>
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-- 
Thanks,
Morgan