[j-nsp] RIB and FIB - Memory for MX with LR

[Mark Tinka]

On Saturday, June 29, 2013 12:25:09 PM Saku Ytti wrote:

> For chassis based boxes something like this[0] could
> potentially allow delaying upgrades by reducing FIB
> demand in WAN facing linecards.

For us, one of the more practical reasons of running MPLS in 
the core (a BGP-free core).

Of course, this pushes pressure out to the edge, but at 
least you aren't sweating (ab)out your core.

Mark.
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