[j-nsp] Trio Bandwidth

[Phil Bedard]

I have the most familiarity with the 16x10GE cards which use 4 Trio chips,
but are similar to the other MPC2 cards.

Each of those Trio chips has 70G of bandwidth shared between the ingress
ports and the fabric like you mentioned.  Traffic going in/out of the same
PFE doesn't count against the 70Gbps, so you can creatively run them at
"line-rate."  

There is also a small limitation with bandwidth from that generation Trio
to/from the fabric.  It's dependent on packet size but it's roughly
37Gbps.  You see this if you have 40G coming from the fabric headed
towards the 4 egress ports.
 
Phil 

On 5/30/14, 5:27 PM, "Saku Ytti" <saku at ytti.fi> wrote:

>On (2014-05-30 11:54 -0700), joel jaeggli wrote:
>
>> the bandwidth is symmetric... the forwarding lookup is only done on the
>> ingress linecard.
>
>(Memory) bandwidth is unidir, single Trio has maybe 70Gbps of memory
>bandwidth
>(it depends on cell alignment, it can be 80Gbps and in artificial scenario
>could be lot less than 70Gbps). So if your ingress is 40Gbps you have only
>30Gbps of egress.
>Lookup performance is about 50-55Mpps, linerate in MPC would require
>60Mpps,
>so bit shy of that. But again, would really only surface in artificial
>scenario.
>On MX80 and MX104 it might plausibly be issue in some esoteric but
>non-artificial scenario, as you have more 10 ports than 4 on Trio.
>
>> larger microcode size
>> 
>> which impacts the availability of some relatively esoteric features...
>
>No. E model has better oscillator for timing shizzle and double the DDR3
>memory on LU chip, which is not going to affect anything as far as I
>know, as
>it was upgraded to support now de-funct mobilenext product.
>
>-- 
>  ++ytti
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