[j-nsp] understand the DRAM usage on CFEB(FEB-M10i-M7i-S)

[Michael Loftis]

It's not quite the FIB, it's a representation of it (J-Tree) for
lookups.  I don't recall much of the specifics past that on the
FEB/CFEB of the M7i/M10i because there's the other memories involved
too and I can't recall how they're used.  But yes the microkernel is
given a digest of the FIB as a j-tree which it keeps a copy of.

On Thu, Oct 1, 2015 at 5:51 AM, Martin T <m4rtntns at gmail.com> wrote:
> One last question- am I correct that copy of FIB is kept on this
> microkernel SDRAM? I mean there seems to be a clear correlation
> between amount of routes in router and CFEB microkernel memory
> utilization. The reason I assume this is because if I upgrade the
> SDRAM SODIMM on CFEB(i.e. upgrade the memory for microkernel), then
> total amount of "heap" memory on CFEB increases and if router has more
> routes, then the usage of "heap" memory increases.
>
>
> thanks,
> Martin
>
> On 9/30/15, Martin T <m4rtntns at gmail.com> wrote:
>> Ok, thanks! I had never seen a solution where parity information is
>> stored in additional individual SDRAM chips. So in conclusion 128MiB
>> of on-board SDRAM is used for packet memory, 64MiB of on-board SDRAM
>> is used for packet memory parity information and replaceable DDR SDRAM
>> SODIMM is used solely for the PFE microkernel.
>>
>>
>> regards,
>> Martin
>>
>> On 9/29/15, Michael Loftis <mloftis at wgops.com> wrote:
>>> The "extra" SDRAM chips.  The packet memory has parity or ECC bits, I
>>> actually do not recall for sure which, but the "extra" is for those
>>> extra bits.
>>>
>>> On Tue, Sep 29, 2015 at 12:45 PM, Martin T <m4rtntns at gmail.com> wrote:
>>>> What do you mean?
>>>>
>>>>
>>>> thanks,
>>>> Martin
>>>>
>>>> On Tue, Sep 29, 2015 at 8:45 PM, Michael Loftis <mloftis at wgops.com>
>>>> wrote:
>>>>> Parity/ECC.
>>>>>
>>>>> On Tue, Sep 29, 2015 at 7:32 AM, Martin T <m4rtntns at gmail.com> wrote:
>>>>>> Hi,
>>>>>>
>>>>>> according to Juniper M10i Compact Forwarding Engine
>>>>>> Board(http://www.juniper.net/techpubs/en_US/release-independent/junos/topics/concept/cfeb-m10i-description.html)
>>>>>> documentation it has 128 MiB SDRAM for packet memory and 128 MiB SDRAM
>>>>>> for the microkernel. If I visually inspect the CFEB, then it has
>>>>>> twelve "MT 46V8M16" DDR SDRAM chips which means 12x 134217728 bits,
>>>>>> i.e. 192MiB of on-board soldered DDR SDRAM. Questions:
>>>>>>
>>>>>> 1) Are four "MT 46V8M16" DDR SDRAM chips actually not in use? If they
>>>>>> are in use, then what for?
>>>>>>
>>>>>> 2) Am I correct that on-board soldered DRAM is used for shared packet
>>>>>> buffer and installable DDR SDRAM SODIMM is used for the microkernel?
>>>>>>
>>>>>>
>>>>>> thanks,
>>>>>> Martin
>>>>>> _______________________________________________
>>>>>> juniper-nsp mailing list juniper-nsp at puck.nether.net
>>>>>> https://puck.nether.net/mailman/listinfo/juniper-nsp
>>>>>
>>>>>
>>>>>
>>>>> --
>>>>>
>>>>> "Genius might be described as a supreme capacity for getting its
>>>>> possessors
>>>>> into trouble of all kinds."
>>>>> -- Samuel Butler
>>>
>>>
>>>
>>> --
>>>
>>> "Genius might be described as a supreme capacity for getting its
>>> possessors
>>> into trouble of all kinds."
>>> -- Samuel Butler
>>>
>>



-- 

"Genius might be described as a supreme capacity for getting its possessors
into trouble of all kinds."
-- Samuel Butler