[j-nsp] Juniper PTX1000

Saku Ytti saku at ytti.fi
Tue Dec 20 14:21:50 EST 2016

On 20 December 2016 at 18:42,  <adamv0025 at netconsultings.com> wrote:

> Both CRS-X and NCS6k are powered by nPower X1e NPU.
> And my understanding is that it's Homogeneous(Same PPE type) MPSoC i.e. Symmetric MultiProcessing (SMP), much like all the chips out there (used in ASR9k or MX and PTX, ...).
> The difference I understand is in the instruction set that the PPE is running.
> And my guess is that threads on each PPE are using run to completion scheduling.
> Let me know your thoughts please.
> And by pipeline with regards to NPU design I understand pipelining of arrays of PPEs where each array in the pipeline consists of PPEs dedicated to a specific function(parse search modify). -like in ASR9k.

Current gen ASR9k, EZchip, is like Trio, ALU FP or Huawei Solar, many
identical cores, fully programmable, essentially you're only limited
by time in what you can do. Where as NCS5k/Arista/Jericho, PTX are
ASIC/pipelines, with much more specialised hardware with lot less
flexibility, but what they do do, they do far more efficiently, which
means denser boxes are pragmatic.
Roughly speaking pipeline/ASIC is great for core, DC, in Edge you
often may require richer features offered by NPU designs, and density
isn't that crucial.


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