[j-nsp] Juniper PTX1000

Saku Ytti saku at ytti.fi
Wed Dec 21 06:04:40 EST 2016

On 21 December 2016 at 12:50, Adam Vitkovsky <Adam.Vitkovsky at gamma.co.uk> wrote:

> What I'm trying to say is that it doesn't matter that much how are the PPEs
> organized on the NPU chip (SMP, Pipeline or even SIMD architecture).

In my vocabulary pipeline means ASIC, not NPU. NPU would have many
identical chips sharing the load, typically running same microcode.
But pipeline would be ASIC with different dedicated chips doing
specific function, and packet traversing them in-order, having very
limited amount of programmability. But going throug the pipeline in
constant time.

The relevancy in these two is that NPU can be reprogrammed by having
the chips execute new microcode, to have it do pretty much anything,
with performance hit. And while pipeline/ASIC may have some
flexibility through recirculation and clever design, there are also
many things it simply won't be able to do.
That is NPU is not that much different than multicore CPU, just
instruction set more geared to networking application, but ultimately
won't do much without the microcode. But pipeline/ASIC will do what
the device is physically wired to do, at great speed and power

I'm sure if you deploy NCS, Arista or PTX to the edge, you'll find
bunch of these things, which just work on ASR9k/MX/SR/NE type devices.
Much like you've seen bunch of these things in 6500/7600 LAN cards,
I'm sure.

More information about the juniper-nsp mailing list