[j-nsp] Juniper PTX1000

[adamv0025 at netconsultings.com]

> Saku Ytti [mailto:saku at ytti.fi]
> Sent: Wednesday, December 21, 2016 11:05 AM
> 
> On 21 December 2016 at 12:50, Adam Vitkovsky
> <Adam.Vitkovsky at gamma.co.uk> wrote:
> 
> > What I'm trying to say is that it doesn't matter that much how are the
> > PPEs organized on the NPU chip (SMP, Pipeline or even SIMD architecture).
> 
> In my vocabulary pipeline means ASIC, not NPU. NPU would have many
> identical chips sharing the load, typically running same microcode.
> But pipeline would be ASIC with different dedicated chips doing specific
> function, and packet traversing them in-order, having very limited amount of
> programmability. But going throug the pipeline in constant time.
> 
In my vocabulary ASIC is not field programmable, but I see your point.

> The relevancy in these two is that NPU can be reprogrammed by having the
> chips execute new microcode, to have it do pretty much anything, with
> performance hit. And while pipeline/ASIC may have some flexibility through
> recirculation and clever design, there are also many things it simply won't be
> able to do.
> That is NPU is not that much different than multicore CPU, just instruction set
> more geared to networking application, but ultimately won't do much
> without the microcode. But pipeline/ASIC will do what the device is physically
> wired to do, at great speed and power efficiency.
> 
This looks like legacy L2 switches, but I think there's very little that is actually hardwired in chips of modern high-end core routers.

My understanding is that on modern boxes, even in the "Pipeline" setup, the "computation element" at each stage of the pipeline is not an ASIC (not even an FPGA) but rather a multithreaded RISC CPU core. (but I see how some of the stages in the pipeline could be realized by FPGAs). 
And the deterministic and fast performance is achieved by limited instruction set optimized for only a subset of packet processing features. (smaller instruction set = faster processing = smaller delta between best & worst case lookup = more deterministic processing time).


adam



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