[j-nsp] Juniper PTX1000
saku at ytti.fi
Wed Dec 21 10:53:05 EST 2016
On 21 December 2016 at 15:56, <adamv0025 at netconsultings.com> wrote:
> This looks like legacy L2 switches, but I think there's very little that is actually hardwired in chips of modern high-end core routers.
> My understanding is that on modern boxes, even in the "Pipeline" setup, the "computation element" at each stage of the pipeline is not an ASIC (not even an FPGA) but rather a multithreaded RISC CPU core. (but I see how some of the stages in the pipeline could be realized by FPGAs).
I believe Jericho, PTX PEchip and very much like 'legacy l2 switches'.
Just fancier and more complicated, but fundamentally the same.
> And the deterministic and fast performance is achieved by limited instruction set optimized for only a subset of packet processing features. (smaller instruction set = faster processing = smaller delta between best & worst case lookup = more deterministic processing time).
NPU certainly is not constant time, in fact there is watchdog
verifying PPE's are not running atypically long, if they are, they are
terminated, so that software bug does not stall, rather destroys that
NPU is very much run-to-completion, you do what microcode asks you,
regardless how long it takes (unless killed by watchdog).
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