[j-nsp] Juniper PTX1000

[adamv0025 at netconsultings.com]

> Saku Ytti [mailto:saku at ytti.fi]
> Sent: Wednesday, December 21, 2016 3:53 PM
> 
> On 21 December 2016 at 15:56,  <adamv0025 at netconsultings.com> wrote:
> 
> > This looks like legacy L2 switches, but I think there's very little that is
> actually hardwired in chips of modern high-end core routers.
> >
> > My understanding is that on modern boxes, even in the "Pipeline" setup,
> the "computation element" at each stage of the pipeline is not an ASIC (not
> even an FPGA) but rather a multithreaded RISC CPU core. (but I see how
> some of the stages in the pipeline could be realized by FPGAs).
> 
> I believe Jericho, PTX PEchip and very much like 'legacy l2 switches'.
> Just fancier and more complicated, but fundamentally the same.
> 
Hard to say, maybe you're right and RISC CPUs are just not fast enough, or there's no need for much versatility to outweigh the increased power consumption, so it's realized by FPGAs. 
I think RISC CPUs are fast enough cause my experience thus far is that all these high capacity core cards are not build for high pps rates, I mean you won't be able to run 64B packets at line-rate.  
Whereas on good edge cards you can and you even have some extra spare so you can enable features. 

> > And the deterministic and fast performance is achieved by limited
> instruction set optimized for only a subset of packet processing features.
> (smaller instruction set = faster processing = smaller delta between best &
> worst case lookup = more deterministic processing time).
> 
> NPU certainly is not constant time, in fact there is watchdog verifying PPE's
> are not running atypically long, if they are, they are terminated, so that
> software bug does not stall, rather destroys that lookup.
> NPU is very much run-to-completion, you do what microcode asks you,
> regardless how long it takes (unless killed by watchdog).
> 
Yeah but I'd like to think that if a PPE can process a packet head in 30-60usec, then you can then set watchdog timeout to 100usec and the delay variance of 70usec between best and worst case is just an invisible noise in the latency/jitter graph(in msec). 


adam


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