[j-nsp] ACX50xx l2circuit counters
saku at ytti.fi
Tue Jun 21 07:31:38 EDT 2016
On 21 June 2016 at 14:23, Mark Tinka <mark.tinka at seacom.mu> wrote:
> Take Policy Map for the MX, for example. I worked with Juniper for 2
> years to develop this feature, and was lucky it could be done on the
> Trio because of that design. They can't do it on any other M-series, for
> instance, and certainly not the DPC's which are external chips. It's not
> a feature they foresaw when developing the Trio, but they managed to
> make it work without sacrificing performance after-the-fact.
You could do it in every NPU, NPU is run-to-completion, you give it
real software to run, and it does something. You're only limited by
All IP/L3 stuff is done on internal I-Chip, evolution from IP2.
EZchip2 is there just for L2, QoS or something like that. Ironically,
the EZchip2 itself could have done it for sure, but perhaps not at an
> When I started testing the ME3600X/3800X in 2009, the Nile chip did not
> support QPPB. After working with Cisco for 6 months, I managed to
> convince them to re-spin the ASIC before they started manufacturing the
> box for general shipping. But such opportunities are few and far between
> (basically, non-existent), and I wouldn't bank on them being the norm,
> ever. Which is why flexibility in the future is easier with an in-house
> chip, even if it's not always guaranteed.
This is absolutely fantastic and BRCM would probably require much
larger volume to respin anything.
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