[j-nsp] what’s the story behind MPC5E

[david.roy at orange.com]

Erratum: it's a 240 Gbps PFE 

-----Message d'origine-----
De : ROY David DTSI/DERS 
Envoyé : vendredi 20 mai 2016 16:24
À : 'Adam Vitkovsky'; juniper-nsp at puck.nether.net
Objet : RE: what’s the story behind MPC5E

MPC5e has one PFE (260Gpbs) made of 2 XM chip, 1 XL and 1 XQ (only for Q mode) 

-----Message d'origine-----
De : juniper-nsp [mailto:juniper-nsp-bounces at puck.nether.net] De la part de Adam Vitkovsky Envoyé : vendredi 20 mai 2016 16:20 À : juniper-nsp at puck.nether.net Objet : [j-nsp] what’s the story behind MPC5E

Hi folks,

Would anyone know what’s the story behind MPC5E (which I think uses one PFE) with Gen 2 TRIO (XM, XL)?
Forwarding capability of up to 130 Gbps per Packet Forwarding Engine.
Up to 240 Gbps of full-duplex traffic.

- Since 240 is not 2x130 it begs the question what components are the bottleneck then?


And to add to the confusion the MPC4E which uses two PFEs with Gen 1.5 TRIO (XM, 2xLU) is rated Up to 260 Gbps of full-duplex traffic.

- Would have thought that Gen 2 TRIO would have better performance or better connectivity to fabric ?


adam














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