[j-nsp] what’s the story behind MPC5E

[Adam Vitkovsky]

> From: Hannes Viertel [mailto:hviertel at juniper.net]
> Sent: Friday, May 20, 2016 4:23 PM
>
> A couple of remarks
>
> It’s more like Gen2 (MPC4) and Gen2,5 (MPC5) trio…
>
Well I'd consider MPC3 and MPC4 as Gen 1.5 because they are somewhere half way between Gen1 (LU+MQ) and Gen2 (XL+XM).


> On MPC5, Each of the two XM complexes is considered a PFE on the MPC5.
> Each XM connects with ~either 3x40G oder 2x60G on a MX960 chassis
> depending on the number of active PFE’s. That’s why it’s considered a 240G
> FDX line card.  The MPC5 comes in two flavours.. 24x10G or 2x100+4x10G …
> so no need to put more horsepowers on the backplane links.
>
So there are no inter XM HSL2 links on the card please?
For it to constitute as two PFEs I would then, as per design, expect there to be a separate set of VOQs per each XM(PFE) so that each XM can backpressure towards ingress LCs independently, is that the case please?
Also how does the backpressure work in this setup when the common XL gets oversubscribed does it signal backpressure to both XMs or does it know which XM is responsible for most of its cycles so it will issue backpressure signal only to that XM?
If the above is not met then I would consider it as a single PFE with two discrete arbiters feeding a common XL (which I think is just asking for trouble).

>
> The MPC4 has also two XM’s and is in all flavours oversubscribed… ( 32x10
> and 2x100+8x10g ). Each PFE is capable of processing ~130g traffic towards
> the backplane. Assuming a base3 chassis and scbe2 in 3+0 active mode, you
> should be able to achieve/come close to your 260g.
>
But MPC4E is kind of vice versa to MPC5e as it has two LU chips hooked up to one XM.
And my understanding is that this ensemble is twice on the card amounting to two discrete PFEs (each with 2xLU and an XM).


adam











        Adam Vitkovsky
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