[j-nsp] MX204 vs. MX240??

[Saku Ytti]

On Tue, 12 Nov 2019 at 06:55, Rob Foehl <rwf at loonybin.net> wrote:

> Atypical only in that there's no chassis switch involved on the Ethernet
> link...  The comment above was about software catching up to what's
> (functionally) missing from the line card, in this case.

I can't parse this, sorry.

> PR1444186 -- GRE packets which are larger than MTU get dropped on MX204
> platforms when sampling is enabled on the egress interface -- was a fun
> one, and as it happens an MX80 was used to demonstrate that the issue was

This is interesting, but not enough information on the PR to make
heads or tails.

MX204 has all the bits and bobs linecard boxes have, just FAB side
serdes is not used for FAB, forwarding in MX204 is no different to
forwarding in linecard box when both ingress and egress port are on
same Trio. So that PR is surprising to me, being MX204 specific.

> specific to MX204.  There's a not-yet-public follow up for that, and I've
> also got a half dozen 204s sporadically timing out BFD sessions, with
> platform as the only commonality.

When this happens, does it affect many BFD sessions at the same time?
There is PR1401507 which causes disruption between the RE PPMd and the
LC CPU PPMd causing all LC PPMd distributed keepalives to be torn
down.
Do you run BFD keepalives from LC CPU or NPU? I don't know if MX204
has real linecard CPU, or if it is like PTX1k where due to cost saving
there is no separate linecard CPU. If that is the case, and you don't
want NPU/inline BFD disabling distributed BFD is actually CPU cheaper
than doing LC CPU and less risky.

-- 
  ++ytti