[nsp] c7200 architecture question?

From: Gert Doering (gert@greenie.muc.de)
Date: Fri Jun 08 2001 - 16:39:57 EDT


Hi,

until today, I was sure that I had read somewhere that the slots 0
(onboard), 1, 3 and 5 of the 7200 routers share one PCI bus (and bandwidth
points), and the slots 2,4, and 6 share a second PCI bus.

Currently I'm reading the Cisco press book "inside cisco IOS software
architecture", and while it focusses on IOS, it also covers different
router architectures in good detail. The book claims in chapter 5 that
the 720x routers have *three* PCI buses, bus 0 for the I/O board
("slot 0"), bus 1 & 2 for the PA slots.

If this is correct, it would mean that I do not have to count "bandwidth
points" for the onboard interfaces when considering PCI bus 0, which makes
a significant difference when using a C7200-I/O-2FE-E or a GE/E that have
400 bandwidth points each.

So... can one of you enlighten me, please? How is the bus architecture of
the 7200s, and which slots affect each other?

thanks!

gert

-- 
USENET is *not* the non-clickable part of WWW!
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Gert Doering - Munich, Germany                             gert@greenie.muc.de
fax: +49-89-35655025                        gert.doering@physik.tu-muenchen.de



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