[c-nsp] GSR OC3 Eng0 to Eng3

[Lamar Owen]

On Tuesday 14 April 2009 10:54:06 Pete Templin wrote:
> Any thoughts on what to look for?

I'm running a 12012 with engine 0 4xOC3c cards here.

The first thing I look for when this sort of things occurs is 'clock source 
line' in the configuration.  I have swapped ports around before and forgotten 
to change the 'clock source internal' to 'clock source line' for the WAN 
OC3's, since I'm also using IR SM OC3's on campus over dark fiber (thus 'clock 
source internal' on both ends of those).  This presents itself as random 
up/down-down/up events when one or both ends of the WAN OC3 are accidentally 
set clock source internal.  Clock source line is supposed to be the default, 
incidentally.  I don't have an ISE 4xOC3 LC to try with for the OSPF flapping 
issues, sorry. 

It's also possible the ADM is sending you a too-hot signal; you can simulate 
an attenuator for testing by slightly pulling the SC for the receive out; this 
simulates an air-gap attenuator.  If you can get an improvement with a slight 
air-gap, it may be too hot from them to you, and you'll need to attenuate.

Have your read 
http://www.cisco.com/en/US/tech/tk482/tk607/technologies_tech_note09186a008009464b.shtml 
(Troubleshooting PSE and NSE Events on POS Interfaces)?  A Positive Stuff Event 
indicates a clock slip somewhere. (or the other things you mentioned; seems 
you have likely read this already.....)

The most revealing line of this is that the POS LC's themselves do not do any 
stuffing, and those path PSE's are being reported by the SONET cloud.  So it 
could be the interstital hop clock slipping.
-- 
Lamar Owen
Chief Information Officer
Pisgah Astronomical Research Institute
1 PARI Drive
Rosman, NC  28772
http://www.pari.edu