[j-nsp] Memory Allocation per FPC

[Igor Gashinsky]

:: Hannes,
:: I have been waiting patiently, Many thanks for this description. It is very 
:: useful, correct me if i am wrong below:
:: 
:: 1. the hardware configuration on the box is Independent of the performance 
:: of the router & I can stick in PICs anywhere
:: 
:: 2. Also even if I am using only 2 FPCs, I can get more performance if I plug 
:: in All the FPCs

Actually, both of the above are (somewhat) incorrect. Since an M series 
will stripe every packet to every FPC, it's relying on the fact that 
statisticly, every FPC has equal probability of having an egress 
interface, and utilize the striping to it's adventage. When there are 
FPC's that have no egress interfaces on them whatsoever, the 
read-from-buffer-on-egress algo will be less efficient (since you are now 
storing packets on FPC's that have 0% probability of having a local egress 
point, and now have to transfer more bits across the fabric per packet) 
and you take a *slight* performance hit on that. Our lab testing has 
shown that hit to be approx 2-3M pps of total forwarding capacity.

So, you should stripe your egress and ingress PICs across FPC's to take 
maximum advantage of the architecture.

Hope this helps,
-igor